1. Field of the Invention
This invention relates to a circuit for detecting/recognizing synchronization pulses of plural formats of multi-frame synchronization on a time-division digital transmission line.
2. Description of the Related Art
As widely known, bit format of a digital transmission is based on a protocol i.e. an agreement. Referring to FIG. 1, a typical format of synchronization bits of a multi-frame synchronization is hereinafter described, to which the present invention is applicable. In the figure, F1 through F20 . . . respectively indicate frame numbers. The period of a single frame is 125 micro second for this case where the sampling frequency is 8 kHz. Each frame consists of as many as n+1 time-slots, TS0 through TSn. The number n+1 is typically 32 for 2.048 Mb/s bit rate, and 128 for 8.048 Mb/s. However, this explanation shall be made for the case where n+1 is 32. Two time-slots, TS0 and TS2, are used for control signals, such as including an enviromental information, alarm signal, etc. or vacant. The balance thirty time-slots are used for voice channels, thus, thirty voice channels plus two control channels, each sampled by 8 kHz, are muliplexed by time division. Each time-slot consists of 8 bits. The first bit of each frame, i.e. the 0-th bit of the first time slot TS0, is for the frame synchronization, recognition of which is carried out by violation of the MD (modified dipulse) code. The technique of this single-frame synchronization and its recognition method have been well known and widely used. Five bits, i.e. the third through 7th bit, of the eight bits of each of the time slots, TS0 and TS2, are further used for above-mentioned control signals, in which the synchronization bits for multi-frame synchronization are included.
A typical layout of the control signals S1 through S30 and the multi-frame synchronization bits, MF and MFn, in a sequential order of the frames are shown in FIG. 2. The multi-frame synchronization bit MF in the figure means "1", as well as MFn means "0". Location of the MF bit in each bit column, b3 through b7, of FIG. 2 is independent from that of each other bit column. However, in a bit column, the MF bit and MFn bit are alternately arranged for every 8-frame sequence, which is of the format promised in advance for the 8-frame synchronization, thus the multi-frame synchronization bits are distinguished from the other signal bits. The number "eight", for example for this case, shall be hereinafter called as a multiplicity number of the multi-frame synchronization.
In FIG. 3, there is shown a typical layout of the control signals S1 through S60 as well as the multi-frame synchronization bits, MF and MFn, and vacants in the same five bits, i.e. the third through 7th bits, for a sequence of the frames of the 16-frame synchronization, where the MF and MFn are alternately arranged for every 16-frame sequence in each bit column. A 20-frame synchronization is also generally used. This frame synchronization having a large multiplicity number, such as 8, 16 or 20, is used for a case where a control signal requiring many bits, such as of a slowly changing information, is transmitted by the bits between the multi-frame synchronize bits MF and MFn, because of its longer cycle time availability . In these figures, the mark "-" indicates vacancy or a spare. The format shown in FIG. 2 is also reported in detail in the magazine "Shisetsu" vol. 34, No. 4, p 75 by NTT (Nippon Telephone & Telegram), in which a digital switching system Model D70 is disclosed. In a practical application field, there is a chance that the local systems each of which having different multiplicity number, such as 8, 16 or 20 as mentioned above, of multi-frame synchronization must be combined into a bigger transmission line. Thus, there can be a digital transmission system in which different kinds, i.e. different multiplicity numbers, of multi-frame synchronization, in other words different numbers of frames for which the synchronization bit, MF or MFn, appears alternately, must be concurrently existing. For example, if an 8-frame synchronization system and a 16-frame synchronization system are combined, the time-slot TS0 is formatted for 8-frame synchronization by the layout of FIG. 2, while the time-slot TS2 is formatted for the 16-frame synchronization by the layout of FIG. 3, as both shown also in FIG. 1. Therefore, a receiving terminal of the system must be ready to detect what type of, i.e. how many multiplicity numbers of, synchronization is involved therein.
A prior art circuit for detecting the multi-frame synchronization bits and its multiplicity number is schematically shown in FIG. 4. In the figure, the transmission line 1 delivers voice signals as well as control signals and multi-frame synchronization bits of the frame format shown in FIG. 2 and 3. For every frame cycle, a timing circuit 4-1 enables the gate 2-1 only during a specific, predetermined, period in which a specific bit is to come in. Thus, only the specific bit of each frame received from the transmission line 1 is outputted by the gate 2-1 to a shift register 6-1 as well as to an exclusive OR gate 8-1. The bit from the gate 2-1 is delayed by the shift register 6-1 by eight frames and outputted from its output terminal Q8, and delivered to the exclusive OR gate 8-1. The exclusive OR gate 8-1 outputs an output signal "1" on terminal 10-1 when the bit directly from the gate 2-1 and the 8-frame-delayed bit from the shift register 6-1 are of different logic value. Therefore, when the output signal "1" on terminal 10-1 is stably outputted on every eight frame-cycle for several times, it means that the bit specified by the timing circuit 4-1 is the multi-frame synchronization bits MF /MFn of an eight- (i.e. multiple-) frame synchronization. In the same way, timing circuits 4-2.about.4-5, gates 2-2.about.2-5, shift registers 6-2.about.6-5, and exclusive OR gates 8-2.about.8-5 are provided, except that the bits specified by the timing circuits are respectively different, each corresponding to the bit b4 through b7. Thus, all the five bits of the b3 through b7 of the time slot TS0 are respectively detected to recognize that the received signals are of 8-frame synchronization.
Then, a second circuit group composed of timing circuits 5-1.about.5-5, gates 3-1.about.3-5, shift registers 7-1.about.7-5, and exclusive OR gates 9-1.about.9-5 is further provided, in the same way as described above, excepting that each timing circuit 5-1 through 5-5 selectively enables each corresponding gate 3-1 through 3-5 at a specific, i.e. predetermined, timing to pass the specific bits, b3 through b7, of the time slot TS2 of each frame. Each shift register 7-1 through 7-5 delays the inputted signal by 16 frames. Therefore, when each of the output signals "1" on terminals 11-1 through 11-5 is stably outputted from respective exclusive OR gates 9-1 through 9-5 on every 16 frame-cycle, it is recognized that the bits specified by the timing circuits 5-1 through 5-5 are the multi-frame synchronization bits MF /MFn of the 16-frame synchronization, as shown in FIG. 3. Thus, it is recognized that there are concurrently existing two kinds of multi-frame synchronization in the received signals.
Summarizing the prior arts for recognizing the multi-frame synchronization bits, the recognition is carried out by the circuit groups, each provided particularly for individual multi-frame synchronization, i.e. so-called wired logic. Therefore, the required number of the circuit groups is increased proportionally to the number of, i.e. how many kinds of, the multi-frame synchronization involved therein are to be detected. This fact increases the cost of the hardware, and reduces the flexibility at the installation or the field service of the hardware.